ENTRY LEVEL WORKER
Joined: 28 May 2013
Posts: 10
|
 Posted: Tue May 28, 2013 10:06 pm Post subject: Power verification is just as important as functional verifi |
| |
SoCs are getting smaller and faster, but smaller node geometries leak more current and higher speed circuitry consumes more power. Yet everyone wants to reduce power consumption.
Analysis of power characteristics and verification of power management functionality have been employed to reconcile these opposing vectors –first at the gate level and then at the RTL. But these approaches fall short for both system level verification and applications that require real world stimulus. With gate level verification, simulations are slow, while debugging is difficult, takes longer and requires more resources. Meanwhile, RTL simulation using directed unit level tests on individual blocks provides neither the completeness nor accuracy required for full chip power verification and analysis.
Because power is impacted by software and hardware, low power verification and power analysis must be done at the system level on the full chip, applying real world applications and long test sequences. Emulators have the speed and capacity to pull in the full design environment, even for 1billion gate designs, apply real world stimuli – including application and embedded software – and run many sequences.
Mentor Graphics' Veloce system has two primary aspects, which can be used together or separately. Low power verification ensures that power management techniques were implemented correctly and that the power functionality of the design is correct. Power analysis calculates average and peak power to help design efficient batteries and to avoid such things as over or under specifying SoC power requirements.
Low power verification
Emulation enables designers to conduct power related verification at the system level with software and hardware running simultaneously. Test sequences can be sent from software and executed by the hardware. Designers can also boot an operating system and stress test the design quickly through a large number of power sequences.
The growing number of SoC power domains is one reason why emulation is essential for complete and accurate low power verification. Only emulation has the speed and capacity to repeatedly exercise a large number of power domains and, because the whole SoC is mapped into the emulator, it can mimic low power functionality using real stimuli, providing a higher confidence in the completeness of verification than is possible with simulation.
Various power management design techniques can minimise power consumption. At a conceptual level, these involve:
• switching off power domains that are not needed for specific SoC functionality to reduce leakage current, and
• creating multiple voltage domains to trade off power requirement and performance
Verifying these low power management techniques have not impacted the design functionality requires modelling and thorough verification of: retention; corruption; isolation; and level shifters. Veloce provides support for all of these verification and modelling tasks
_________________
Car insurance comparison |
|
FAQ
Search
Memberlist
Usergroups
Profile
Log in to check your private messages
Log in
Register
